Rethinking How XPUs Connect At Scale
Rethinking How XPUs Connect At Scale
Plaid is building a modular scale-up fabric that integrates XPUs more tightly within a system
The Problem
Compute is scaling. Connectivity isn’t.
Compute is scaling. Connectivity isn’t.
Every generation delivers more compute, more memory bandwidth, and more powerful XPUs. But connecting those XPUs still depends on an increasingly complex hierarchy of boards, switches, retimers, cables, connectors, and optics.
As systems scale, more of the power, cost, latency, and physical complexity moves into the network between processors.
The result: the system spends more resources moving data instead of computing.
Every generation delivers more compute, more memory bandwidth, and more powerful XPUs. But connecting those XPUs still depends on an increasingly complex hierarchy of boards, switches, retimers, cables, connectors, and optics.
As systems scale, more of the power, cost, latency, and physical complexity moves into the network between processors.
The result: the system spends more resources moving data instead of computing.
The Solution
Collapse the scale‑up network.
Collapse the scale‑up network.
Plaid’s Rack‑on‑Package architecture brings multiple XPUs together through a tightly integrated, high‑bandwidth fabric—replacing layers of local system connectivity with much shorter XPU‑to‑XPU links.
Instead of redesigning the processor, Plaid starts with existing XPUs and integrates the system around them. Compute, memory, power, cooling and connectivity come together as a modular scale‑up platform.
The result: more direct connectivity between XPUs, with less infrastructure in between.
Plaid’s Rack‑on‑Package architecture brings multiple XPUs together through a tightly integrated, high‑bandwidth fabric—replacing layers of local system connectivity with much shorter XPU‑to‑XPU links.
Instead of redesigning the processor, Plaid starts with existing XPUs and integrates the system around them. Compute, memory, power, cooling and connectivity come together as a modular scale‑up platform.
The result: more direct connectivity between XPUs, with less infrastructure in between.
Impact
System-Level Efficiency Gains
System-Level Efficiency Gains
More Efficient Interconnect
Short-reach package links enable far lower energy per bit.
Lower XPU-to-XPU Latency
Direct package-level links replace longer board / cable / switch paths.
Lower Scale-Up BOM
Switches, cables, connectors and components are reduced or eliminated.
Supported By
OUR AMAZING TEAM
